Research

My work spans cryptographic privacy, hardware acceleration, and AI for chip design. A unifying theme is making theory deployable — every project targets real hardware implementations, not just algorithmic results.

Agentic AI for Chip Design

LLM Agents for EDARTL DebuggingFormal VerificationTestbench GenerationCoverage ClosureChipSage Labs

This is what I'm working on full-time at ChipSage Labs. Chip design today takes 36 to 42+ months from architecture to tapeout, and first-pass silicon success rates have collapsed to around 14%. We think agentic AI can compress that dramatically. ChipSage is built around four specialized agents: SageAnalyze pinpoints root causes in RTL and simulation logs; SageExecute generates reversible RTL patches and UVM testbench updates; SageLearn uses RL-based optimization for PPA and timing closure; and SageAudit keeps an immutable record of every AI action for tapeout confidence. The moat is data: we've collected 1M+ proprietary chip error data points through global competitions at venues like NDSS, ISQED, and ICCD, and through academic partnerships. The flywheel is that more usage generates richer error context, which trains better agents, which attracts more partners. Our MVP is deployed at 10+ universities, early adopters see 45% average speedup in design cycles, and we've raised $3M in grants from NSF, DARPA, and the Air Force.

Privacy-Preserving Computation

Zero-Knowledge ProofsFully Homomorphic EncryptionSecure Multi-Party ComputationPrivacy in Federated LearningZK-Friendly Hash FunctionsNeural Network Ownership

Most of my PhD work lives here. The through-line is taking cryptographic privacy tools that work in theory and making them fast enough to actually deploy. That has meant building ZK-friendly hash functions from scratch (AMAZE, Gotta Hash 'Em All), designing systems for privacy and robustness in federated learning (zPROBE, ZORRO), proving neural network ownership with ZKPs (ZKROWNN), and benchmarking the ZKP framework landscape so people know what to actually use. Hardware/software co-design runs through all of it: I build FPGA prototypes to validate that things work at scale, not just on paper.

Related Publications

  1. PAC to the Future: Zero-Knowledge Proofs of PAC Private Systems

    G. Repetto, N. Sheybani, G. De Micheli, F. Koushanfar

    ACM WWW 2026 Workshop on ZKP and Blockchain for Web 4.0

  2. Robust and Secure Code Watermarking for Large Language Models via ML/Crypto Codesign

    R. Zhang*, N. Javidnia*, N. Sheybani, F. Koushanfar

    Preprint, 2026

  3. ZORRO: Zero-Knowledge Attested Client-Side Backdoor Defense in Split Learning

    N. Sheybani*, A. Pegoraro*, J. Knauer*, E. Mollakuqe, P. Rieger, F. Koushanfar, A. Sadeghi

    ACM CCS 2025

  4. Optimizing Privacy-Preserving Primitives to Support LLM-Scale Applications

    Y. Jandali, R. Zhang, N. Sheybani, F. Koushanfar

    ICCAD 2025

  5. Zero-Knowledge Proof Frameworks: A Systematic Survey

    N. Sheybani, A. Ahmed, M. Kinsy, F. Koushanfar

    Preprint, 2025

  6. You Can Have Your Cake and Eat It Too: Ensuring Practical Robustness and Privacy in Federated Learning

    N. Sheybani, F. Koushanfar

    AAAI Spring Symposium Series, 2024

  7. zPROBE: Zero Peek Robustness Checks for Federated Learning

    Z. Ghodsi*, M. Javaheripi*, N. Sheybani*, X. Zhang*, K. Huang, F. Koushanfar

    ICCV 2023

  8. ZKROWNN: Zero Knowledge Right of Ownership for Neural Networks

    N. Sheybani, Z. Ghodsi, R. Kapila, F. Koushanfar

    DAC 2023

  9. zPROBE: Zero Peek Robustness Checks for Federated Learning

    Z. Ghodsi*, M. Javaheripi*, N. Sheybani*, X. Zhang*, K. Huang, F. Koushanfar

    NeurIPS TSRML Workshop 2022· Outstanding Paper Award

Scalable Hardware for Security and Privacy

FPGA AccelerationFHE Hardware (DARPA DPRIVE)ZK Hash ArchitecturesHW/SW Co-designSecure Embedded SystemsResource-Efficient Inference

A lot of crypto research stops at "this is fast on a CPU." I build custom hardware to find out what actually happens when you push these workloads onto FPGAs. Projects include FPGA acceleration for FHE (part of the DARPA DPRIVE program at Intel Labs), hashing architectures for ZKP backends (AMAZE, Gotta Hash 'Em All), neural network watermarking on FPGAs (FastStamp), and resource-efficient inference (Tailor). The recurring question is: what does it take to go from a cryptographic construction to something you can run on real hardware at scale?

Related Publications

  1. Optimizing Privacy-Preserving Primitives to Support LLM-Scale Applications

    Y. Jandali, R. Zhang, N. Sheybani, F. Koushanfar

    ICCAD 2025

  2. Gotta Hash 'Em All! Speeding Up Hash Functions for Zero-Knowledge Proof Applications

    N. Sheybani*, T. Gong, A. Ahmed, N. Njungle, M. Kinsy, F. Koushanfar

    ICCAD 2025

  3. AMAZE: Accelerated MiMC Architecture for Accelerating Zero-Knowledge Applications on the Edge

    A. Ahmed*, N. Sheybani*, D. Moreno, N. Njungle, T. Gong, M. Kinsy, F. Koushanfar

    ICCAD 2024· Top Picks in Hardware and Embedded Security 2025

  4. Tailor: Altering Skip Connections for Resource-Efficient Inference

    O. Weng, J. Loroch, N. Sheybani, J. Liang, A. Tumeo, J. Weisz, R. Kastner

    IEEE TRETS, 2023

  5. FastStamp: Accelerating Neural Steganography and Digital Watermarking of Images on FPGAs

    S. Hussain*, N. Sheybani*, P. Neekhara*, X. Zhang, J. Duarte, F. Koushanfar

    ICCAD 2022

  6. SenseHash: Computing on Sensor Values Mystified at the Origin

    N. Sheybani, X. Zhang, S. U. Hussain, F. Koushanfar

    IEEE TETC, 2022

  7. Is Revolutionary Hardware for Fully Homomorphic Encryption important? What else is needed?

    C. Bonte, R. Cammarota, J. Cheon, W. Dai, N. Gama, S. Halevi, D. Joo, M. Kim, K. Laine, T. Lepoint, H. Naehrig, D. Micciancio, N. Sheybani, Y. Polyakov, L. Shen, J. Yang

    COSADE 2021